1. Field of the Invention.
The present invention relates to the field of CMOS integrated circuits.
2. Prior Art.
Integrated circuits such as operational amplifiers and the like are normally provided with an output stage for coupling to and driving whatever additional device or devices may be connected thereto in a particular application wherein the operational amplifier or other device is used. To be suitable for broad application, it is generally preferred to provide such output stages with various characteristics, some or all of which may be important in various applications. By way of example, in devices such as operational amplifiers, it is preferable to have a relatively large and symmetrical output swing, preferably rail to rail, though at least comprising a substantial portion of the supply voltage. It is also desirable to have the output relatively symmetrical, and able to both source and sink a substantial amount of current for driving loads having a significant capacitive component, yet dissipating relatively low quiescent power to minimize power consumption when not driving such loads in the same or different applications. Obviously various other characteristics such as stability, manufacturability, etc. are also important considerations.
The design of a suitable output stage in bi-polar technology is relatively easy, in that a push-pull NPN-PNP emitter follower stage may be used. If one attempts to apply the same concept to a CMOS output stage however, replacing NPN-PNP transistors with N Channel and P Channel FETs, the resulting output stage exhibits poor performance. In particular, the output stage will require about 3 volts of head room so that with a 5 volt supply, the output voltage swing is only approximately 2 volts, or approximately 40 percent of the supply. Another alternative is to use a vertical NPN emitter follower with a current source attached to its emitter. This reduces the head room to approximately a volt but the drive is very asymmetric, the output stage having a strong source current capability but a weak sink current capability.
Most commercial CMOS operational amplifiers use a third approach, namely a pair of output FETs, one being P-channel and the other N-channel. By having their drains connected together, the source of the P-channel device connected to the positive power supply line and the source of the N-channel device connected to the negative power supply line, such an output stage gives rail to rail swing at least under no load conditions. However the trick is in driving the gates of the two FETs appropriately.
A typical output stage in accordance with the prior art is shown in FIG. 1. Although there are several variations of the figure shown, all generally behave similarly. The output current I.sub.0 is just NI.sub.A -NI.sub.B. It will be noted that P2 is N times larger than P1, N2 is K times larger than N1 and N4 is N times larger than N3. EQU I.sub.0 =N(I.sub.A -I.sub.B)=N(I.sub.A -(2I-KI.sub.A)) EQU I.sub.0 =N[(1+K)I.sub.A -2I) I.sub.A .gtoreq.0 EQU Typically, K=1 EQU Then I.sub.0 =2N(I.sub.A -I)
In any case, maximum negative drive is -2NI (when I.sub.A =0). When I.sub.0 =0, I.sub.A =2I/(1+K) and the current consumption of the stage is: ##EQU1##
The ratio of maximum negative drive current to quiescent current is: ##EQU2##
For typical values of K=1 and N=20, this ratio is ##EQU3## with the theoretical maximum being 2:1. Therefore to provide a lot of negative drive capability, the output stage must be operated at a high quiescent current.